1. Field of the Invention
This invention relates to a semiconductor circuit device and, more particularly, to a semiconductor circuit device comprising a protection element to protect the circuit from ESD and so on.
2. Description of a Related Art
In a semiconductor circuit device, it is necessary to electrically isolate each element in order that no electrical interference occurs between the plurality of elements formed on the substrate or within the substrate. There are increasingly strict demands for semiconductor circuit devices with higher integration levels, greater functionality, faster speed, and lower power consumption, and various element isolation techniques have been proposed in the past. One of the most representative element isolation methods is the LOCOS (LOCal Oxidation of Silicon) structure. In the LOCOS method, elements are isolated by forming a thermal oxide layer between elements on the substrate, using a nitride film as a mask. By performing such oxidation, the oxidation progresses toward the silicon substrate interior, and a buried oxide layer (LOCOS) is formed.
The STI (Shallow Trench Isolation) method is known as another element isolation technique. In the STI method, a groove or trench is formed in silicon by dry etching, and after filling the trench with SiO2, CMP (Chemical Mechanical Polishing) is used to remove SiO2 formed outside the trench. An isolation structure is thereby formed in which a flat oxide layer is buried only in the trench. Compared with a LOCOS structure, STI makes possible smaller isolation widths, thus greatly contributing to higher device densities.
The SOI (Silicon On Insulator) structure is known as an isolation technique which includes the substrate itself. A SOI structure comprises a device formed in a silicon thin film (SOI layer) on an insulating layer. In a bulk CMOS device, a P/N-type MOS transistor is isolated by a well layer; but an SOI-MOS device is isolated by the Si supporting substrate and a buried oxide layer, as shown in FIG. 8. A device in which the SOI layer is made thin and the body area below the channel is completely depleted is called a fully depleted SOI device; a device having an area which is not depleted to the bottom of the body area is called a partially depleted SOI device. FIG. 8 shows one example of the structure of a partially depleted SOI device. In this structure, each element is isolated by, for example, a LOCOS oxide layer, and the operating area (SOI layer) is completely isolated by an insulator.
The SOI structure is effective for solving problems such as latch-up and parasitic junction capacitance, and greatly contributes to increases in device density and speed and to reduced power consumption. However, the buried oxide layer causes some problems. While the buried oxide layer provides electrical isolation, it also impedes thermal conduction, greatly reducing heat dissipation. This effect cannot be ignored, particularly for elements with high current densities.
An NMOS device with the gate connected to ground (GGNMOS, Gate-Grounded NMOS) is known as a protective element which prevents internal breakdown in a circuit due to ESD (Electro-Static Discharge). ESD gives rise to a surge voltage pulse between an external connection pad and the internal circuit due to contact of the semiconductor circuit device with, for example, human skin or equipment. A GGNMOS element prevents application of a surge voltage to a gate electrode of the internal circuit by passing a current between the external pad and the ground line as a result of breakdown between source and drain. In the SOI structure of a protective element, there is the problem that thermal conduction is impeded by the buried oxide layer, so that the temperature of the ESD protective element rises sharply due to the surge current, and the ESD withstand voltage of the ESD protection element itself is reduced.
Consequently, proposals have been made to resolve the heat dissipation problems of SOI elements (see for example U.S. Pat. No. 6,352,882). Polysilicon plugs penetrating the buried oxide layer are formed on the substrate, connecting the MOSFET device region with the silicon substrate of an opposite polarity type. The polysilicon plugs are in contact with the MOSFET device source or drain, and comprise the function of diffusing positive or negative ESD. At the same time, the polysilicon plugs comprise the function of diffusing heat, and can prevent thermal breakdown of the element. However, such a structure has the problem of involving complicated manufacturing processes.
On the other hand, a shield plate isolation method is known as a technique for electrically isolating elements (see for example Japanese Unexamined Patent Application Publication No. 11-126899). This technique provides, for example, an oxide layer and a shield plate electrode so as to surround the element. By applying a reverse bias voltage to the shield plate, extension of the depletion layer outside the region surrounded by the shield plate electrode is prevented, and electrical isolation of elements is achieved.
However, such shield plate electrodes have not been studied from the standpoint of thermal problems on an SOI substrate (or in SOI elements). In particular, the problem of thermal breakdown in elements used for input protection, and their relation to shield plate electrodes, have not received any study. Further, the devices disclosed in the above references comprise straight gate electrodes intersecting with the shield plate electrode; there is a considerable possibility that this intersection portion may also constitute a major problem with respect to ESD. Or, because the diffusion layer connected to the external terminal is isolated by the shield plate electrode, the discharge path cross-sectional area is small, and the amount of ESD is small.
In a transistor used as a protection element, in order to render uniform the current distribution, a gate electrode structure comprising a waffle-shape pattern layout has been proposed (see for example Japanese Unexamined Patent Application Publication No. 6-112482). By means of a waffle-shape pattern gate electrode, the current density of the breakdown current flowing between source and drain is made uniform, so that the electrostatic breakdown intensity of the protection element can be enhanced. However, the problems of such gate electrode structures and of drops in electrostatic resistance due to heat of the protection element have not yet received any study.